收藏本站
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read (1,2,3)
t WC
ADDR "A"
MATCH
R/ W "A"
DATA IN "A"
ADDR "B"
DATA OUT "B"
(1)
t WP
t DW
VALID
MATCH
t WDD
t AW
VALID
NOTES:
t DDD
2720 drw 10
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CE L = CE R = V IL. OE "B" = V IL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
OE
t AS (6)
CE
R/ W
t AW
t WP (2)
t WR (3)
t HZ (7)
t LZ
DATA OUT
(7)
t WZ (7)
(4)
t DW
t OW
t DH
t HZ (7)
(4)
DATA IN
NOTES:
2720 drw 11
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE =V IL and R/ W = V IL .
3. t WR is measured from the earlier of CE or R/ W going to V IH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the bus
for the required t DW . If OE = V IH during an R /W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
9
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
IDT7140LA55C IC SRAM 8KBIT 55NS 48DIP
IDT7142LA55C IC SRAM 16KBIT 55NS 48DIP
IDT7143LA25G IC SRAM 32KBIT 25NS 68PGA
IDT7164L25YGI IC SRAM 64KBIT 25NS 28SOJ
IDT71T75802S200PFGI IC SRAM 18MBIT 200MHZ 100TQFP
IDT71T75902S85BGG IC SRAM 18MBIT 85NS 119BGA
IDT71V016SA12PHGI IC SRAM 1MBIT 12NS 44TSOP
IDT71V124SA10PHGI IC SRAM 1MBIT 10NS 32TSOP
相关代理商/技术参数
IDT7134LA25JI8 功能描述:IC SRAM 32KBIT 25NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI
IDT7134LA25P 功能描述:IC SRAM 32KBIT 25NS 48DIP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI
IDT7134LA25PDGI 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 25NS 48DIP
IDT7134LA35CB 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 35NS SB48
IDT7134LA35FB 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 32KBIT 35NS 48FPACK
IDT7134LA35J 功能描述:IC SRAM 32KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI
IDT7134LA35J8 功能描述:IC SRAM 32KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI
IDT7134LA35JI 制造商:Integrated Device Technology Inc 功能描述: